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d a t a sh eet product speci?cation supersedes data of 2002 feb 18 2002 jun 06 integrated circuits 74ahc1g79; 74ahct1g79 single d-type flip-flop; positive-edge trigger
2002 jun 06 2 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 features symmetrical output impedance high noise immunity esd protection: C hbm eia/jesd22-a114-a exceeds 2000 v C mm eia/jesd22-a115-a exceeds 200 v C cdm eia/jesd22-c101 exceeds 1000 v. low power dissipation balanced propagation delays multiple very small 5 pin packages output capability: standard specified from - 40 to +125 c. description the 74ahc1g/ahct1g79 is a high-speed si-gate cmos device. the 74ahc1g/ahct1g79 provides a single positive-edge triggered d-type flip-flop. information on the data input is transferred to the q output on the low-to-high transition of the clock pulse. the d input must be stable one set-up time prior to the low-to-high clock transition for predictable operation. quick reference data gnd = 0 v; t amb =25 c; t r =t f 3.0 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i +(c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts. 2. the condition is v i = gnd to v cc . symbol parameter conditions typical unit ahc1g ahct1g t phl /t plh propagation delay cp to q c l = 15 pf; v cc = 5 v 3.5 3.5 ns c i input capacitance 1.5 1.5 pf c pd power dissipation capacitance c l = 50 pf; f = 1 mhz; notes 1 and 2 15 16 pf
2002 jun 06 3 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 function table see note 1. note 1. h = high voltage level; l = low voltage level; - = low-to-high cp transition; x = dont care; q + 1 = state after the next low-to-high cp transition. inputs output cp d q + 1 - ll - hh lxq ordering information pinning type number package temperature range pins package material code marking 74ahc1g79gw - 40 to +125 c 5 sc-88a plastic sot353 ap 74ahct1g79gw - 40 to +125 c 5 sc-88a plastic sot353 cp 74AHC1G79GV - 40 to +125 c 5 sc-74a plastic sot753 a79 74ahct1g79gv - 40 to +125 c 5 sc-74a plastic sot753 c79 pin symbol description 1 d data input d 2 cp clock pulse input cp 3 gnd ground (0 v) 4 q data output q 5v cc supply voltage
2002 jun 06 4 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 fig.1 pin configuration. handbook, halfpage 1 2 3 5 4 mna439 79 v cc cp q gnd d fig.2 logic symbol. handbook, halfpage mna440 2 1 cp d4 q fig.3 iec logic symbol. handbook, halfpage mna441 2 14 fig.4 logic diagram. handbook, full pagewidth mna442 cp d c c c c c c c c c tg tg tg tg q c
2002 jun 06 5 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). note 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. symbol parameter conditions 74ahc1g 74ahct1g unit min. typ. max. min. typ. max. v cc supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 v v i input voltage 0 - 5.5 0 - 5.5 v v o output voltage 0 - v cc 0 - v cc v t amb operating ambient temperature see dc and ac characteristics per device - 40 +25 +125 - 40 +25 +125 c t r ,t f ( d t/ d f) input rise and fall times v cc = 3.3 0.3 v -- 100 --- ns/v v cc =5 0.5 v -- 20 -- 20 ns/v symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i ik input diode current v i < - 0.5 v -- 20 ma i ok output diode current v o < - 0.5 or v o >v cc + 0.5 v; note 1 - 20 ma i o output source or sink current - 0.5v 2002 jun 06 6 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 dc characteristics family 74ahc1g at recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions t amb ( c) unit other v cc (v) 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v ih high-level input voltage 2.0 1.5 -- 1.5 - 1.5 - v 3.0 2.1 -- 2.1 - 2.1 - v 5.5 3.85 -- 3.85 - 3.85 - v v il low-level input voltage 2.0 -- 0.5 - 0.5 - 0.5 v 3.0 -- 0.9 - 0.9 - 0.9 v 5.5 -- 1.65 - 1.65 - 1.65 v v oh high-level output voltage v i =v ih or v il ; i o = - 50 m a 2.0 1.9 2.0 - 1.9 - 1.9 - v v i =v ih or v il ; i o = - 50 m a 3.0 2.9 3.0 - 2.9 - 2.9 - v v i =v ih or v il ; i o = - 50 m a 4.5 4.4 4.5 - 4.4 - 4.4 - v v i =v ih or v il ; i o = - 4.0 ma 3.0 2.58 -- 2.48 - 2.40 - v v i =v ih or v il ; i o = - 8.0 ma 4.5 3.94 -- 3.8 - 3.70 - v v ol low-level output voltage v i =v ih or v il ; i o =50 m a 2.0 - 0 0.1 - 0.1 - 0.1 v v i =v ih or v il ; i o =50 m a 3.0 - 0 0.1 - 0.1 - 0.1 v v i =v ih or v il ; i o =50 m a 4.5 - 0 0.1 - 0.1 - 0.1 v v i =v ih or v il ; i o = 4.0 ma 3.0 -- 0.36 - 0.44 - 0.55 v v i =v ih or v il ; i o = 8.0 ma 4.5 -- 0.36 - 0.44 - 0.55 v i li input leakage current v i =v cc or gnd 5.5 -- 0.1 - 1.0 - 2.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 1.0 - 10 - 40 m a c i input capacitance - 1.5 10 - 10 - 10 pf
2002 jun 06 7 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 family 74ahct1g at recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions t amb ( c) unit other v cc (v) 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v ih high-level input voltage 4.5 to 5.5 2.0 -- 2.0 - 2.0 - v v il low-level input voltage 4.5 to 5.5 -- 0.8 - 0.8 - 0.8 v v oh high-level output voltage v i =v ih or v il ; i o = - 50 m a 4.5 4.4 4.5 - 4.4 - 4.4 - v v i =v ih or v il ; i o = - 8.0 ma 4.5 3.94 -- 3.8 - 3.70 - v v ol low-level output voltage v i =v ih or v il ; i o =50 m a 4.5 - 0 0.1 - 0.1 - 0.1 v v i =v ih or v il ; i o = 8.0 ma 4.5 -- 0.36 - 0.44 - 0.55 v i li input leakage current v i =v ih or v il 5.5 -- 0.1 - 1.0 - 2.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 1.0 - 10 - 40 m a d i cc additional quiescent supply current per input pin v i = 3.4 v; other inputs at v cc or gnd; i o =0 5.5 -- 1.35 - 1.5 - 1.5 ma c i input capacitance - 1.5 10 - 10 - 10 pf
2002 jun 06 8 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 ac characteristics type 74ahc1g79 gnd = 0 v; t r =t f 3.0 ns. notes 1. typical values are measured at v cc = 3.3 v. 2. typical values are measured at v cc = 5.0 v. type 74ahct1g79 gnd = 0 v; t r =t f 3.0 ns. note 1. typical values are measured at v cc =5v. symbol parameter test conditions t amb ( c) unit waveforms c l (pf) 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v cc = 3.0 to 3.6 v; note 1 t phl /t plh propagation delay cp to q see figs 5 and 6 15 - 4.9 8.4 1.0 9.8 1.0 11.5 ns 50 - 6.9 12.0 1.0 14.0 1.0 15.5 ns v cc = 4.5 to 5.5 v; note 2 t phl /t plh propagation delay cp to q see figs 5 and 6 15 - 3.5 5.6 1.0 7.0 1.0 8.0 ns 50 - 5.1 8.0 1.0 10.0 1.0 11.0 ns t su set-up time d to cp 3.0 1.0 - 3.0 - 4.0 - ns t h hold time d to cp +2.0 - 1.0 - 2.0 - 3.0 - ns t w clock pulse width high or low 3.0 -- 3.0 - 4.0 - ns f max maximum clock pulse frequency 90 -- 90 - 70 - mhz symbol parameter test conditions t amb ( c) unit waveforms c l (pf) 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v cc = 4.5 to 5.5 v; note 1 t phl /t plh propagation delay cp to q see figs 5 and 6 15 - 3.5 5.0 1.0 6.0 1.0 8.0 ns 50 - 5.0 8.0 1.0 10.0 1.0 11.0 ns t su set-up time d to cp 3.0 1.0 - 3.0 - 4.0 - ns t h hold time d to cp +2.0 - 1.0 - 0 - 3.0 - ns t w clock pulse width high or low 3.0 -- 3.0 - 4.0 - ns f max maximum clock pulse frequency 90 -- 90 - 70 - mhz
2002 jun 06 9 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 ac waveforms fig.5 the clock pulse (cp) to output (q) propagation delays. family v i input requirements v m input v m output ahc1g gnd to v cc 50% v cc 50% v cc ahct1g gnd to 3.0 v 1.5 v 50% v cc handbook, full pagewidth mna443 cp input q output t phl t plh v m v m v oh v i gnd d input v i gnd v ol v m v m fig.6 load circuitry for switching times. handbook, halfpage v cc v i v o mna101 d.u.t. c l r t pulse generator definitions for test circuit: c l = load capacitance including jig and probe capacitance (see chapter ac characteristics). r t = termination resistance should be equal to the output impedance z 0 of the pulse generator.
2002 jun 06 10 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 package outlines references outline version european projection issue date iec jedec eiaj sot353 wb m b p d e 1 e a a 1 l p q detail x h e e v m a a b y 0 1 2 mm scale c x 13 2 4 5 plastic surface mounted package; 5 leads sot353 unit a 1 max b p cd e (2) e 1 h e l p qy w v mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.1 0.2 dimensions (mm are the original dimensions) 0.45 0.15 0.25 0.15 a 1.1 0.8 97-02-28 sc-88a
2002 jun 06 11 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 references outline version european projection issue date iec jedec jeita sot753 sc-74a wb m b p d e a a 1 l p q detail x h e e v m a a b y 0 1 2 mm scale c x 13 2 4 5 plastic surface mounted package; 5 leads sot753 unit a 1 b p cd e h e l p qy w v mm 0.100 0.013 0.40 0.25 3.1 2.7 0.26 0.10 1.7 1.3 e 0.95 3.0 2.5 0.2 0.1 0.2 dimensions (mm are the original dimensions) 0.6 0.2 0.33 0.23 a 1.1 0.9 02-04-16
2002 jun 06 12 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 jun 06 13 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2002 jun 06 14 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 jun 06 15 philips semiconductors product speci?cation single d-type ?ip-?op; positive-edge trigger 74ahc1g79; 74ahct1g79 notes
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/04/pp 16 date of release: 2002 jun 06 document order number: 9397 750 09712

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